Texas Instruments AFE79 Series - 2.12.8 Register 62 h (offset = 62 h) [reset = 8 h]; 2.12.9 Register 64 h (offset = 64 h) [reset = 0 h]; 2.12.10 Register 65 h (offset = 65 h) [reset = 0 h]

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Serial Interface Register Maps
Table 2-1222. Register 60 Field Descriptions
Bit Field Type Reset Description
3-0
TX_DUC_ASYNC_
FIFO_CONFIG0
R/W 0h
Pointer offset value for FIFO0.
Valid range: 0 to 15
2.12.8 Register 62h (offset = 62h) [reset = 8h]
Figure 2-1211. Register 62h
7 6 5 4 3 2 1 0
TX_DUC_ASYNC_FIFO_CONFIG1
R/W-8h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1223. Register 62 Field Descriptions
Bit Field Type Reset Description
3-0
TX_DUC_ASYNC_
FIFO_CONFIG1
R/W 8h
Pointer offset value for FIFO1.
Valid range: 0 to 11
2.12.9 Register 64h (offset = 64h) [reset = 0h]
Figure 2-1212. Register 64h
7 6 5 4 3 2 1 0
TX_DUC_FIFO_CONFIG0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1224. Register 64 Field Descriptions
Bit Field Type Reset Description
4-0
TX_DUC_FIFO_C
ONFIG0
R/W 0h
TX DUC FIFO Configuration0. Value dependent on
interplation factor, DAC rate, etc.
Optimal value automatically determined if System
Configuration Macros are used.
2.12.10 Register 65h (offset = 65h) [reset = 0h]
Figure 2-1213. Register 65h
7 6 5 4 3 2 1 0
TX_DUC_FIFO_CONFIG1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1225. Register 65 Field Descriptions
Bit Field Type Reset Description
2-0
TX_DUC_FIFO_C
ONFIG1
R/W 0h
TX DUC FIFO Configuration1. Value dependent on
interplation factor, DAC rate, etc.
Optimal value automatically determined if System
Configuration Macros are used.