Texas Instruments AFE79 Series - 2.5.164 Register F5 h (offset = F5 h) [reset = 0 h]; 2.5.165 Register F6 h (offset = F6 h) [reset = 0 h]; 2.5.166 Register F8 h (offset = F8 h) [reset = 0 h]; 2.5.167 Register F9 h (offset = F9 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.164 Register F5h (offset = F5h) [reset = 0h]
Figure 2-660. Register F5h
7 6 5 4 3 2 1 0
0 0 0 0 SERDES_FIFO_WR_PTR_SAMPLE
R/W-0h R/W-0h R/W-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-665. Register F5 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-0
SERDES_FIFO_W
R_PTR_SAMPLE
R 0h
2.5.165 Register F6h (offset = F6h) [reset = 0h]
Figure 2-661. Register F6h
7 6 5 4 3 2 1 0
0 0 0 SERDES_FIFO_RD_PTR_SAMPLE 0
R/W-0h R/W-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-666. Register F6 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-1
SERDES_FIFO_R
D_PTR_SAMPLE
R 0h
stores the serdes fifo read ptr value when
SERDES_FIFO_PTR_SAMPLE is 1
0-0 0 R/W 0h Must read or write 0
2.5.166 Register F8h (offset = F8h) [reset = 0h]
Figure 2-662. Register F8h
7 6 5 4 3 2 1 0
JESD_INTERNAL_CTR_ON_SYNC_DEASSERT0[7:0]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-667. Register F8 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_INTERNAL_
CTR_ON_SYNC_D
EASSERT0[7:0]
R 0h multiframe counter value on sync_n deassertion at STX1/5
2.5.167 Register F9h (offset = F9h) [reset = 0h]
Figure 2-663. Register F9h
7 6 5 4 3 2 1 0
0 0 0 JESD_INTERNAL_CTR_ON_SYNC_DEASSERT0[12:8]
R/W-0h R/W-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset