Texas Instruments AFE79 Series - 2.5.40 Register 4 Eh (offset = 4 Eh) [reset = 1 h]; 2.5.41 Register 4 Fh (offset = 4 Fh) [reset = 0 h]; 2.5.42 Register 50 h (offset = 50 h) [reset = 1 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.40 Register 4Eh (offset = 4Eh) [reset = 1h]
Figure 2-536. Register 4Eh
7 6 5 4 3 2 1 0
0 0 0 JESD_CLK_RX2_DIV_M
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-541. Register 4E Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
JESD_CLK_RX2_
DIV_M
R/W 1h
M value of jesd divider.
Output of this divider, clock frequency should match STX2/6
rate i.e. lane _rate/40 or lane_rate/33
2.5.41 Register 4Fh (offset = 4Fh) [reset = 0h]
Figure 2-537. Register 4Fh
7 6 5 4 3 2 1 0
0 0 0 JESD_CLK_RX2_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-542. Register 4F Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
JESD_CLK_RX2_
DIV_N_M1
R/W 0h
N-1 value of jesd divider.
Output of this divider, clock frequency should match STX2/6
rate i.e. lane _rate/40 or lane_rate/33
2.5.42 Register 50h (offset = 50h) [reset = 1h]
Figure 2-538. Register 50h
7 6 5 4 3 2 1 0
0 0 0 JESD_CLK_FB_DIV_M
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-543. Register 50 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
JESD_CLK_FB_DI
V_M
R/W 1h
M value of jesd divider.
Output of this divider, clock frequency should match STX
3,4/7,8 rates i.e. lane _rate/40 or lane_rate/33