JESD_SUBCHIP Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.3.63 Register 6Fh (offset = 6Fh) [reset = 76h]
Figure 2-104. Register 6Fh
7 6 5 4 3 2 1 0
RXOCTETPATH7_CLK_SEL RXOCTETPATH6_CLK_SEL
R/W-7h R/W-6h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-107. Register 6F Field Descriptions
Bit Field Type Reset Description
6-4
RXOCTETPATH7_
CLK_SEL
R/W 7h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX8.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
RXOCTETPATH6_
CLK_SEL
R/W 6h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX7.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2.3.64 Register 78h (offset = 78h) [reset = 0h]
Figure 2-105. Register 78h
7 6 5 4 3 2 1 0
ADC_DATA_G
ATING_DIS_FB
CD
ADC_DATA_G
ATING_DIS_FB
AB
ADC_DATA_G
ATING_DIS_R
XD
ADC_DATA_G
ATING_DIS_R
XC
ADC_DATA_G
ATING_DIS_R
XB
ADC_DATA_G
ATING_DIS_R
XA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-108. Register 78 Field Descriptions
Bit Field Type Reset Description
5-5
ADC_DATA_GATI
NG_DIS_FBCD
R/W 0h
FOR LOW POWER CONSUMPTION:
0 - enable data gating of FBCD data based on Rx_ON/FB_ON
signals
1 - disable data gating of FBCD data based on
Rx_ON/FB_ON signals
4-4
ADC_DATA_GATI
NG_DIS_FBAB
R/W 0h
FOR LOW POWER CONSUMPTION:
0 - enable data gating of FBAB data based on Rx_ON/FB_ON
signals
1 - disable data gating of FBAB data based on Rx_ON/FB_ON
signals
3-3
ADC_DATA_GATI
NG_DIS_RXD
R/W 0h
FOR LOW POWER CONSUMPTION:
0 - enable data gating of RXD data based on Rx_ON/FB_ON
signals
1 - disable data gating of RXD data based on Rx_ON/FB_ON
signals
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