www.ti.com
ADC JESD Register Map
409
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.5.67 Register 74h (offset = 74h) [reset = 0h]
Figure 2-563. Register 74h
7 6 5 4 3 2 1 0
LINK0_DID
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-568. Register 74 Field Descriptions
Bit Field Type Reset Description
7-0 LINK0_DID R/W 0h JESD link config for STX1/5
2.5.68 Register 75h (offset = 75h) [reset = 0h]
Figure 2-564. Register 75h
7 6 5 4 3 2 1 0
LINK0_ADJCNT LINK0_BID
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-569. Register 75 Field Descriptions
Bit Field Type Reset Description
7-4 LINK0_ADJCNT R/W 0h JESD link config for STX1/5
3-0 LINK0_BID R/W 0h JESD link config for STX1/5
2.5.69 Register 76h (offset = 76h) [reset = 0h]
Figure 2-565. Register 76h
7 6 5 4 3 2 1 0
0 LINK0_ADJDIR LINK0_PHADJ 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-570. Register 76 Field Descriptions
Bit Field Type Reset Description
7-7 0 R/W 0h Must read or write 0
6-6 LINK0_ADJDIR R/W 0h JESD link config for STX1/5
5-5 LINK0_PHADJ R/W 0h JESD link config for STX1/5
4-0 0 R/W 0h Must read or write 0
2.5.70 Register 77h (offset = 77h) [reset = 1h]
Figure 2-566. Register 77h
7 6 5 4 3 2 1 0
LINK0_SCR 0 0 LINK0_ILA_L_M1
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset