ADC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-588. Register 8A Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
LINK0_ERR_CNT_
CLR
R/W 0h
Config for STX1/5
Clears the JESD sync_n error counter
2.5.88 Register 8Ch (offset = 8Ch) [reset = 0h]
Figure 2-584. Register 8Ch
7 6 5 4 3 2 1 0
LINK1_DID
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-589. Register 8C Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_DID R/W 0h JESD link config for STX2/6
2.5.89 Register 8Dh (offset = 8Dh) [reset = 0h]
Figure 2-585. Register 8Dh
7 6 5 4 3 2 1 0
LINK1_ADJCNT LINK1_BID
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-590. Register 8D Field Descriptions
Bit Field Type Reset Description
7-4 LINK1_ADJCNT R/W 0h JESD link config for STX2/6
3-0 LINK1_BID R/W 0h JESD link config for STX2/6
2.5.90 Register 8Eh (offset = 8Eh) [reset = 0h]
Figure 2-586. Register 8Eh
7 6 5 4 3 2 1 0
0 LINK1_ADJDIR LINK1_PHADJ 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-591. Register 8E Field Descriptions
Bit Field Type Reset Description
7-7 0 R/W 0h Must read or write 0
6-6 LINK1_ADJDIR R/W 0h JESD link config for STX2/6
5-5 LINK1_PHADJ R/W 0h JESD link config for STX2/6
4-0 0 R/W 0h Must read or write 0