Texas Instruments AFE79 Series - 2.6.118 Register 49 D5 h (offset = 49 D5 h) [reset = 60 h]; 2.6.119 Register 49 D8 h (offset = 49 D8 h) [reset = 0 h]; 2.6.120 Register 49 D9 h (offset = 49 D9 h) [reset = 60 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.6.118 Register 49D5h (offset = 49D5h) [reset = 60h]
Figure 2-832. Register 49D5h
7 6 5 4 3 2 1 0
RX_AGCBUFDAC_LANE2 RX_SLICER_BIAS_LANE2[2:1]
R/W-3h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-838. Register 49D5 Field Descriptions
Bit Field Type Reset Description
7-5
RX_AGCBUFDAC_
LANE2
R/W 3h Controls AGC output driver for lane 3.
1-0
RX_SLICER_BIAS
_LANE2[2:1]
R/W 0h Controls the RX slicer bias setting for lane 3.
2.6.119 Register 49D8h (offset = 49D8h) [reset = 0h]
Figure 2-833. Register 49D8h
7 6 5 4 3 2 1 0
RX_SLICER_BI
AS_LANE1[0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-839. Register 49D8 Field Descriptions
Bit Field Type Reset Description
7-7
RX_SLICER_BIAS
_LANE1[0]
R/W 0h Controls the RX slicer bias setting for lane 2.
2.6.120 Register 49D9h (offset = 49D9h) [reset = 60h]
Figure 2-834. Register 49D9h
7 6 5 4 3 2 1 0
RX_AGCBUFDAC_LANE1 RX_SLICER_BIAS_LANE1[2:1]
R/W-3h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-840. Register 49D9 Field Descriptions
Bit Field Type Reset Description
7-5
RX_AGCBUFDAC_
LANE1
R/W 3h Controls AGC output driver for lane 2.
1-0
RX_SLICER_BIAS
_LANE1[2:1]
R/W 0h Controls the RX slicer bias setting for lane 2.