Texas Instruments AFE79 Series - 2.4.51 Register 52 h (offset = 52 h) [reset = 0 h]; 2.4.52 Register 53 h (offset = 53 h) [reset = 0 h]; 2.4.53 Register 54 h (offset = 54 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-283. Register 51 Field Descriptions
Bit Field Type Reset Description
7-0
COMMA_ALIGN_D
LY_THRESH
R/W FFh UNUSED
2.4.51 Register 52h (offset = 52h) [reset = 0h]
Figure 2-280. Register 52h
7 6 5 4 3 2 1 0
LINK1_DID
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-284. Register 52 Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_DID R/W 0h Lane configuration
2.4.52 Register 53h (offset = 53h) [reset = 0h]
Figure 2-281. Register 53h
7 6 5 4 3 2 1 0
LINK1_BID LINK1_ADJCNT
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-285. Register 53 Field Descriptions
Bit Field Type Reset Description
7-4 LINK1_BID R/W 0h Lane configuration
3-0 LINK1_ADJCNT R/W 0h Lane configuration
2.4.53 Register 54h (offset = 54h) [reset = 0h]
Figure 2-282. Register 54h
7 6 5 4 3 2 1 0
LINK1_ADJDIR LINK1_PHADJ
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-286. Register 54 Field Descriptions
Bit Field Type Reset Description
6-6 LINK1_ADJDIR R/W 0h Lane configuration
5-5 LINK1_PHADJ R/W 0h Lane configuration