Texas Instruments AFE79 Series - 2.4.61 Register 5 Ch (offset = 5 Ch) [reset = 80 h]; 2.4.62 Register 5 Dh (offset = 5 Dh) [reset = 0 h]; 2.4.63 Register 5 Eh (offset = 5 Eh) [reset = 0 h]

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Serial Interface Register Maps
Table 2-293. Register 5B Field Descriptions (continued)
Bit Field Type Reset Description
4-0 LINK1_ILA_S_M1 R/W 0h
JESD S-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
2.4.61 Register 5Ch (offset = 5Ch) [reset = 80h]
Figure 2-290. Register 5Ch
7 6 5 4 3 2 1 0
LINK1_ILA_HD LINK1_CF
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-294. Register 5C Field Descriptions
Bit Field Type Reset Description
7-7 LINK1_ILA_HD R/W 1h
JESD HD configuration value used only for ILA checking; may
be set independently of the actual JESD mode
4-0 LINK1_CF R/W 0h Lane configuration
2.4.62 Register 5Dh (offset = 5Dh) [reset = 0h]
Figure 2-291. Register 5Dh
7 6 5 4 3 2 1 0
LINK1_RES1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-295. Register 5D Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_RES1 R/W 0h Lane configuration
2.4.63 Register 5Eh (offset = 5Eh) [reset = 0h]
Figure 2-292. Register 5Eh
7 6 5 4 3 2 1 0
LINK1_RES2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-296. Register 5E Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_RES2 R/W 0h Lane configuration