Texas Instruments AFE79 Series - 2.6.115 Register 49 D0 h (offset = 49 D0 h) [reset = 0 h]; 2.6.116 Register 49 D1 h (offset = 49 D1 h) [reset = 60 h]; 2.6.117 Register 49 D4 h (offset = 49 D4 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-834. Register 49CD Field Descriptions
Bit Field Type Reset Description
7-5
TX_VREG_IBIAS_
LANE0
R/W 4h
This register is effective only when per-lane register 0xF4[9]=1
(pu_himode_vddr)
1-0
TX_VREG_IBIAS_
LANE1[2:1]
R/W 0h
This register is effective only when per-lane register 0xF4[9]=1
(pu_himode_vddr)
2.6.115 Register 49D0h (offset = 49D0h) [reset = 0h]
Figure 2-829. Register 49D0h
7 6 5 4 3 2 1 0
RX_SLICER_BI
AS_LANE3[0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-835. Register 49D0 Field Descriptions
Bit Field Type Reset Description
7-7
RX_SLICER_BIAS
_LANE3[0]
R/W 0h Controls the RX slicer bias setting for lane 4.
2.6.116 Register 49D1h (offset = 49D1h) [reset = 60h]
Figure 2-830. Register 49D1h
7 6 5 4 3 2 1 0
RX_AGCBUFDAC_LANE3 RX_SLICER_BIAS_LANE3[2:1]
R/W-3h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-836. Register 49D1 Field Descriptions
Bit Field Type Reset Description
7-5
RX_AGCBUFDAC_
LANE3
R/W 3h Controls AGC output driver for lane 4.
1-0
RX_SLICER_BIAS
_LANE3[2:1]
R/W 0h Controls the RX slicer bias setting for lane 4.
2.6.117 Register 49D4h (offset = 49D4h) [reset = 0h]
Figure 2-831. Register 49D4h
7 6 5 4 3 2 1 0
RX_SLICER_BI
AS_LANE2[0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-837. Register 49D4 Field Descriptions
Bit Field Type Reset Description
7-7
RX_SLICER_BIAS
_LANE2[0]
R/W 0h Controls the RX slicer bias setting for lane 3.