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Texas Instruments AFE79 Series - 2.4.87 Register 76 h (offset = 76 h) [reset = 1 Ch]; 2.4.88 Register 77 h (offset = 77 h) [reset = 20 h]

Texas Instruments AFE79 Series
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DAC JESD Register Map
293
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-319. Register 75 Field Descriptions
Bit Field Type Reset Description
7-7 MATCH_CTRL R/W 1h
For JESDB : When asserted the match character is a
CONTROL character instead of a DATA character.
JESDC : UNUSED
6-6 MATCH_SPECIFIC R/W 1h
For JESDB : Match a specific charater to start the JESD
buffering when asserted; otherwise the first non-K will start the
buffering.
JESDC : UNUSED
5-4 JESD_TEST_SEQ R/W 0h
JESDB:Set to select and verify link layer test sequences. The
error for these sequences comes out the lane alarms bit0. 1=
fail and 0 = pass.
JESDC : UNUSED
0 : test sequence disabled
1 : verify repeating D.21.5 high frequency pattern for random
jitter
2 : verify repeating K.28.5 mixed frequency pattern for
deterministic jitter
3 : verify repeating ILA sequence
3-3
DISABLE_ERR_R
EPORT
R/W 0h
Assertion means that errors will not be reported on the sync_n
output.
2-2 MP_LINK_ENA R/W 0h UNUSED
1-1 NO_LANE_SYNC R/W 0h
Assert if the TX side does not support lane initialization. This
way the RX wont flag errors in the configuration portion of the
ILA.
0-0
MIN_LATENCY_E
NA
R/W 0h This is needed for subclass 0 support.
2.4.87 Register 76h (offset = 76h) [reset = 1Ch]
Figure 2-316. Register 76h
7 6 5 4 3 2 1 0
MATCH_DATA
R/W-1Ch
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-320. Register 76 Field Descriptions
Bit Field Type Reset Description
7-0 MATCH_DATA R/W 1Ch
For JESDB : The character to match for buffer release.
Normally it is a /R/=/K28.0/=0x1C but with these bits the user
can program the value.
JESDC : UNUSED
2.4.88 Register 77h (offset = 77h) [reset = 20h]
Figure 2-317. Register 77h
7 6 5 4 3 2 1 0
SYNC_REQUEST_PULSE_EXPANSION_COUNT
R/W-20h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-321. Register 77 Field Descriptions
Bit Field Type Reset Description
7-0
SYNC_REQUEST_
PULSE_EXPANSI
ON_COUNT
R/W 20h TESTMODE

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