Texas Instruments AFE79 Series User Manual

ADC JESD Register Map www.ti.com
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-655. Register DB Field Descriptions
Bit Field Type Reset Description
7-2 0 R/W 0h Must read or write 0
1-0
SCR_64B_INITVAL
[57:56]
R/W 1h
58 bit inital value used by 64b scrambler (1+x^39+x^58)
Relevant for JESD-C
2.5.155 Register E0h (offset = E0h) [reset = 0h]
Figure 2-651. Register E0h
7 6 5 4 3 2 1 0
0 0 SAMPLE_DROP_MODE_FB SAMPLE_DROP_MODE_RX2 SAMPLE_DROP_MODE_RX1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-656. Register E0 Field Descriptions
Bit Field Type Reset Description
7-6 0 R/W 0h Must read or write 0
5-4
SAMPLE_DROP_
MODE_FB
R/W 0h
0 - No sample drop
1 - sample drop by 2
2 - sample drop by 3
3 - sample drop by 4
3-2
SAMPLE_DROP_
MODE_RX2
R/W 0h
0 - No sample drop
1 - sample drop by 2
2 - sample drop by 3
3 - sample drop by 4
1-0
SAMPLE_DROP_
MODE_RX1
R/W 0h
0 - No sample drop
1 - sample drop by 2
2 - sample drop by 3
3 - sample drop by 4
2.5.156 Register E1h (offset = E1h) [reset = 6h]
Figure 2-652. Register E1h
7 6 5 4 3 2 1 0
0 0 0 0 RXA_SD_CLK_DIV_N_M1 RXA_SD_CLK_DIV_M
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-657. Register E1 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-2
RXA_SD_CLK_DIV
_N_M1
R/W 1h
If input is 2 samples per clk:
SD by 2 -> M=1, N=1
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=2
if input is 1 sample per clk:
SD by 2 -> M=1, N=2
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=4

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English