EasyManuals Logo

Texas Instruments AFE79 Series User Manual

Texas Instruments AFE79 Series
1268 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #239 background imageLoading...
Page #239 background image
www.ti.com
JESD_SUBCHIP Register Map
239
SBAU337May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.3.141 Register 160h (offset = 160h) [reset = 0h]
Figure 2-182. Register 160h
7 6 5 4 3 2 1 0
DBG_DDC_AFI
FO_DBG_LOGI
C_EN
DBG_FBCD_A
FIFO_DBG_CF
G_CLR
DBG_FBAB_A
FIFO_DBG_CF
G_CLR
DBG_RXD_AFI
FO_DBG_CFG
_CLR
DBG_RXC_AFI
FO_DBG_CFG
_CLR
DBG_RXB_AFI
FO_DBG_CFG
_CLR
DBG_RXA_AFI
FO_DBG_CFG
_CLR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-185. Register 160 Field Descriptions
Bit Field Type Reset Description
7-7
DBG_DDC_AFIFO
_DBG_LOGIC_EN
R/W 0h
By default all async fifo debug logic, i.e. clk/syref sticky bit
monitors and fifo overflow/underflow are inactive and clock
gated.
Set this bit to 1, to enable debug logic.
5-5
DBG_FBCD_AFIF
O_DBG_CFG_CLR
R/W 0h To reset sysref and clock sticky bits of rrf-jesd async fifo
4-4
DBG_FBAB_AFIF
O_DBG_CFG_CLR
R/W 0h To reset sysref and clock sticky bits of rrf-jesd async fifo
3-3
DBG_RXD_AFIFO
_DBG_CFG_CLR
R/W 0h To reset sysref and clock sticky bits of rrf-jesd async fifo
2-2
DBG_RXC_AFIFO
_DBG_CFG_CLR
R/W 0h To reset sysref and clock sticky bits of rrf-jesd async fifo
1-1
DBG_RXB_AFIFO
_DBG_CFG_CLR
R/W 0h To reset sysref and clock sticky bits of rrf-jesd async fifo
0-0
DBG_RXA_AFIFO
_DBG_CFG_CLR
R/W 0h To reset sysref and clock sticky bits of rrf-jesd async fifo
2.3.142 Register 161h (offset = 161h) [reset = 0h]
Figure 2-183. Register 161h
7 6 5 4 3 2 1 0
DBG_FIFO_SEL DBG_CFG_FIF
O_PTR_SAMP
LE
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-186. Register 161 Field Descriptions
Bit Field Type Reset Description
7-5 DBG_FIFO_SEL R/W 0h
Select Async. FIFO to read the sampled points from, and
update to status registers dbg_fifo_samples_*_ptr
0 : RX A
1 : RX B
2 : RX C
3 : RX D
4 : FB A
5 : FB C
0-0
DBG_CFG_FIFO_
PTR_SAMPLE
R/W 0h
When 1, pointers are sampled and saved in registers
dbg_fifo_sampled_*_ptr

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Texas Instruments AFE79 Series and is the answer not in the manual?

Texas Instruments AFE79 Series Specifications

General IconGeneral
BrandTexas Instruments
ModelAFE79 Series
CategoryControl Unit
LanguageEnglish

Related product manuals