Texas Instruments AFE79 Series - 2.5.47 Register 58 h (offset = 58 h) [reset = 41 h]; 2.5.48 Register 59 h (offset = 59 h) [reset = 55 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-547. Register 56 Field Descriptions (continued)
Bit Field Type Reset Description
1-0
CTRL_DDC_RD_C
LK_RX1
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
2.5.47 Register 58h (offset = 58h) [reset = 41h]
Figure 2-543. Register 58h
7 6 5 4 3 2 1 0
CTRL_JESD_CLK_RX2_P2 CTRL_JESD_CLK_RX2_P0 CTRL_JESD_CLK_RX1_P2 CTRL_JESD_CLK_RX1_P0
R/W-1h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-548. Register 58 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_JESD_CLK_
RX2_P2
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
5-4
CTRL_JESD_CLK_
RX2_P0
R/W 0h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
3-2
CTRL_JESD_CLK_
RX1_P2
R/W 0h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
1-0
CTRL_JESD_CLK_
RX1_P0
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
2.5.48 Register 59h (offset = 59h) [reset = 55h]
Figure 2-544. Register 59h
7 6 5 4 3 2 1 0
CTRL_JESD_CLK_DIV2_RX1_P
0
CTRL_JESD_CLK_FB_P3 CTRL_JESD_CLK_FB_P1 CTRL_JESD_CLK_FB_P0
R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset