Texas Instruments AFE79 Series - 2.10.10 Register D4 h (offset = D4 h) [reset = 1 h]; 2.10.11 Register D5 h (offset = D5 h) [reset = 32 h]; 2.10.12 Register D8 h (offset = D8 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-1125. Register D0 Field Descriptions
Bit Field Type Reset Description
2-0 GAIN_CTRL R/W 3h
Selection register for the mode in which Rx DSA gain is set.
Following are different values and their meanings:
000 : reserved
001 : 8-pin agc
010 : internal agc
011 : spi_agc
100 : FDSA
101 : 4-Pin mode
110 : reserved
111 : reserved
2.10.10 Register D4h (offset = D4h) [reset = 1h]
Figure 2-1116. Register D4h
7 6 5 4 3 2 1 0
EXT_LNA_CON_EN_RX
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1126. Register D4 Field Descriptions
Bit Field Type Reset Description
1-0
EXT_LNA_CON_E
N_RX
R/W 1h
Enable mask for LNA bypass. The default value is 01 which
means a single lna is enabled. The default need not be
changed for typical use cases.
2.10.11 Register D5h (offset = D5h) [reset = 32h]
Figure 2-1117. Register D5h
7 6 5 4 3 2 1 0
MAX_ANA_ATTN
R/W-32h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1127. Register D5 Field Descriptions
Bit Field Type Reset Description
5-0 MAX_ANA_ATTN R/W 32h
Maximum analog attenuation. Code 51 corresponds to
protection code.
2.10.12 Register D8h (offset = D8h) [reset = 0h]
Figure 2-1118. Register D8h
7 6 5 4 3 2 1 0
DSA_LNA_SW
_MODE
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset