JESD_SUBCHIP Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-141. Register AB Field Descriptions
Bit Field Type Reset Description
7-0
FB_CLK_LFSR_SE
ED_VAL[23:16]
R/W EFh
lfsr seed value. Need to be used along with
'fb_clk_lfsr_seed_load' register
2.3.98 Register ACh (offset = ACh) [reset = 10h]
Figure 2-139. Register ACh
7 6 5 4 3 2 1 0
TX_CLK_DIV_VAL_ACC_THRESH
R/W-10h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-142. Register AC Field Descriptions
Bit Field Type Reset Description
5-0
TX_CLK_DIV_VAL
_ACC_THRESH
R/W 10h Accumulator threshold, while running dithered mode
2.3.99 Register ADh (offset = ADh) [reset = ABh]
Figure 2-140. Register ADh
7 6 5 4 3 2 1 0
TX_CLK_LFSR_SEED_VAL[7:0]
R/W-ABh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-143. Register AD Field Descriptions
Bit Field Type Reset Description
7-0
TX_CLK_LFSR_SE
ED_VAL[7:0]
R/W ABh
lfsr seed value. Need to be used along with
'tx_clk_lfsr_seed_load' register
2.3.100 Register AEh (offset = AEh) [reset = CDh]
Figure 2-141. Register AEh
7 6 5 4 3 2 1 0
TX_CLK_LFSR_SEED_VAL[15:8]
R/W-CDh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-144. Register AE Field Descriptions
Bit Field Type Reset Description
7-0
TX_CLK_LFSR_SE
ED_VAL[15:8]
R/W CDh
lfsr seed value. Need to be used along with
'tx_clk_lfsr_seed_load' register