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SBAU337–May 2020
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Serial Interface Register Maps
2.14.131 Register 4A4h (offset = 4A4h) [reset = 0h]
Figure 2-2014. Register 4A4h
7 6 5 4 3 2 1 0
FB_AGC_RES
ET_LOOP_AT_
SIG_INVALID
FB_AGC_DEC
AY_DETS_RE
SET_AT_RX_O
N
FB_AGC_ATTA
CK_DETS_RE
SET_AT_RX_O
N
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2028. Register 4A4 Field Descriptions
Bit Field Type Reset Description
2-2
FB_AGC_RESET_
LOOP_AT_SIG_IN
VALID
R/W 0h
Bit to control if during RX OFF(and Gain Swap) whether to
reset the loop [start the DSA with default] or freeze the loop.
1-1
FB_AGC_DECAY_
DETS_RESET_AT
_RX_ON
R/W 0h
If enabled, decay detectors get reset during RX OFF(and Gain
Swap) with default state, else they carry over the previous
state
0-0
FB_AGC_ATTACK
_DETS_RESET_A
T_RX_ON
R/W 0h
If enabled, Attack detectors get reset during RX OFF(and Gain
Swap) with default state, else they carry over the previous
state
2.14.132 Register 4A6h (offset = 4A6h) [reset = 1h]
Figure 2-2015. Register 4A6h
7 6 5 4 3 2 1 0
FB_AGC_RES
ET_DETS_GAI
N_CHANGE
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2029. Register 4A6 Field Descriptions
Bit Field Type Reset Description
0-0
FB_AGC_RESET_
DETS_GAIN_CHA
NGE
R/W 1h
For external AGC only. Whether to reset detectors whenever
there is a gain change pulse or not.
2.14.133 Register 4A8h (offset = 4A8h) [reset = 2h]
Figure 2-2016. Register 4A8h
7 6 5 4 3 2 1 0
FB_AGC_BLANK_TIME_FOR_EXT_COMP_CHANGE[7:0]
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2030. Register 4A8 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_BLANK_
TIME_FOR_EXT_
COMP_CHANGE[7
:0]
R/W 2h
When Ext Component Gain Changes, this blanking time is
used for all the detectors
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