DAC JESD Register Map
www.ti.com
294
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.89 Register 78h (offset = 78h) [reset = FFh]
Figure 2-318. Register 78h
7 6 5 4 3 2 1 0
LINK0_SYNC_REQUEST_ENA
R/W-FFh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-322. Register 78 Field Descriptions
Bit Field Type Reset Description
7-0
LINK0_SYNC_RE
QUEST_ENA
R/W FFh
These bits select which errors cause a sync request for
lanes[0:1]/[2:3]. Sync requests take priority over the error
notification; so if sync request isnt desired; set these bits to a
'0';.
Each of the bits for the above mentioned lane errors are
mapped to :
bit7 = JESDB: multiframe alignment error
bit6 = JESDB: frame alignment error
bit5 = JESDB: link configuration error
bit4 = JESDB: elastic buffer overflow (bad RBD value)
bit3 = JESDB: elastic buffer match error. The first non-/K/
doesnt match 'match_ctrl' and 'match_data' programmed
values
bit2 = JESDB: code synchronization error
bit1 = JESDB: 8b/10b not-in-table code error
Bit0 = JESDB: 8b/10b disparity error
bit7 = JESDC: EoEMB alignment error
bit6 = JESDC: EoMB alignment error
bit5 = JESDC: cmd-data in crc mode not matching with spi
register bits
bit4 = JESDC: elastic buffer overflow (bad RBD value)
bit3 = JESDC: TIED to 0.
bit2 = JESDC: extended multiblock alignment error
bit1 = JESDC: sync-header invalid error ('11' or '00' received
in expected sync header location)
Bit0 = JESDC: sync-header CRC error
2.4.90 Register 79h (offset = 79h) [reset = FFh]
Figure 2-319. Register 79h
7 6 5 4 3 2 1 0
LINK1_SYNC_REQUEST_ENA
R/W-FFh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
To Next Page
Loading...
