Texas Instruments AFE79 Series - 2.4.183 Register EFh (offset = EFh) [reset = 0 h]; 2.4.184 Register F0 h (offset = F0 h) [reset = 0 h]; 2.4.185 Register F1 h (offset = F1 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.4.183 Register EFh (offset = EFh) [reset = 0h]
Figure 2-412. Register EFh
7 6 5 4 3 2 1 0
SERDES_RXBCLK_FLAG VALID_DATA_OUT_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-416. Register EF Field Descriptions
Bit Field Type Reset Description
7-4
SERDES_RXBCLK
_FLAG
R 0h serdes_rxbclk_lane[0:3]_monitor_flag
3-0
VALID_DATA_OUT
_FLAG
R 0h JESDB/C:valid_data_out_lane[0:3]/[4:7]_monitor_flag
2.4.184 Register F0h (offset = F0h) [reset = 0h]
Figure 2-413. Register F0h
7 6 5 4 3 2 1 0
TX_DAC_SYSREF_FLAG TX_DAC_CLK_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-417. Register F0 Field Descriptions
Bit Field Type Reset Description
7-4
TX_DAC_SYSREF
_FLAG
R 0h tx_dac_sysref monitor flag
3-0
TX_DAC_CLK_FL
AG
R 0h tx_dac_clk monitor flag
2.4.185 Register F1h (offset = F1h) [reset = 0h]
Figure 2-414. Register F1h
7 6 5 4 3 2 1 0
JESD_SYSREF_TX1_FLAG JESD_CLK_TX1_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-418. Register F1 Field Descriptions
Bit Field Type Reset Description
7-4
JESD_SYSREF_T
X1_FLAG
R 0h jesd_rx_sysref monitor flag
3-0
JESD_CLK_TX1_F
LAG
R 0h jesd_rx_clk monitor flag