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Timing Controller Register Map
973
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-2265. Register B6 Field Descriptions
Bit Field Type Reset Description
1-0
ENABLE_FB_GAIN
_SWAP_CD
R/W 0h
Acts as a enable for gain swap for the fbcd channel. If a bit is
1, then the corresponding rxgswap bit is used, else it is made
0. For eg '11' uses both bits of rxgswap as fbgswap. '10' uses
only MSB of rxgswap for fbgswap etc
2.15.44 Register B8h (offset = B8h) [reset = 0h]
Figure 2-2251. Register B8h
7 6 5 4 3 2 1 0
BROADCAST_
FBNCOSEL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2266. Register B8 Field Descriptions
Bit Field Type Reset Description
0-0
BROADCAST_FBN
COSEL
R/W 0h
Setting this to '1' broadcast to both fbs, the same 2 bit input
ncosel. So the modes supported are:
if broadcast_fbncosel==0:
fbAB: [0 0 ns1 ns0], fbCD: [0,0,ns2,ns1]
if broadcast_fbncosel==1:
fbAB: [ns3 ns2 ns1 ns0], fbCD: [ns3 ns2 ns1 ns0]
Other modes may be achieved by using enable_fbncosel and
force_fbncosel bits below. For example if we want
independent single bit control for both fbs, then make
broadcast_fbncosel=0 and enable_fbncosel_ab & cd to 0 for
the MSB 3 bits
2.15.45 Register B9h (offset = B9h) [reset = 0h]
Figure 2-2252. Register B9h
7 6 5 4 3 2 1 0
FORCE_FBNCOSEL_AB
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2267. Register B9 Field Descriptions
Bit Field Type Reset Description
3-0
FORCE_FBNCOS
EL_AB
R/W 0h
This may be used in the shared tdd mode to distinguish
between fbncosel and rxncosel. Program this to "1000" to
make fb look differently from rx.
2.15.46 Register BAh (offset = BAh) [reset = 0h]
Figure 2-2253. Register BAh
7 6 5 4 3 2 1 0
FORCE_FBNCOSEL_CD
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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