IO Wrap Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.16.488 Register 8BDh (offset = 8BDh) [reset = 2h]
Figure 2-2751. Register 8BDh
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TDD_EN_T
XB
OVR_INTPI_T
DD_EN_TXB
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2767. Register 8BD Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TDD_EN_TXB
R/W 1h
control to select whether the input function intpi_tdd_en_txb
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TDD_
EN_TXB
R/W 0h override value for ovr_sel_intpi_tdd_en_txb is made high
2.16.489 Register 8C0h (offset = 8C0h) [reset = 0h]
Figure 2-2752. Register 8C0h
7 6 5 4 3 2 1 0
SEL_INTPI_TDD_EN_TXC POL_INTPI_TD
D_EN_TXC
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2768. Register 8C0 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_TDD_
EN_TXC
R/W 0h
select control for intpi_tdd_en_txc. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_TDD_
EN_TXC
R/W 0h
polarity control for intpi_tdd_en_txc. 0 indicates pass through
from GPIO when selected 1 indicates inverted signal
2.16.490 Register 8C1h (offset = 8C1h) [reset = 2h]
Figure 2-2753. Register 8C1h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TDD_EN_T
XC
OVR_INTPI_T
DD_EN_TXC
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2769. Register 8C1 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TDD_EN_TXC
R/W 1h
control to select whether the input function intpi_tdd_en_txc
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TDD_
EN_TXC
R/W 0h override value for ovr_sel_intpi_tdd_en_txc is made high
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