Texas Instruments AFE79 Series - 2.4.126 Register A0 h (offset = A0 h) [reset = 0 h]; 2.4.127 Register A1 h (offset = A1 h) [reset = 0 h]

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Serial Interface Register Maps
Table 2-358. Register 9D Field Descriptions
Bit Field Type Reset Description
7-7
LINK1_RELEASE_
OPPORTUNITY_PI
PE_DLY_OVR
R/W 0h TESTMODE
6-6
LINK1_MAPPER_
RESET
R/W 0h TESTMODE
4-0
LINK1_RELEASE_
OPPORTUNITY_PI
PE_DLY_VAL
R/W 0h TESTMODE
2.4.126 Register A0h (offset = A0h) [reset = 0h]
Figure 2-355. Register A0h
7 6 5 4 3 2 1 0
JESD_SH_STATE
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-359. Register A0 Field Descriptions
Bit Field Type Reset Description
7-0 JESD_SH_STATE R 0h
JESDB: K28.5 SEARCH_PATTERN_STATE value
JESDC: SYNC_HEADER SEARCH_PATTERN_STATE value
bits(1:0) = SRX1/5
bits(3:2) = SRX2/6
bits(5:4) = SRX3/7
bits(7:6) = SRX4/8
For stable link, the bits for each lane enabled should read as
"10"
Note: Refer to the TI application note for details on error
interpretation.
2.4.127 Register A1h (offset = A1h) [reset = 0h]
Figure 2-356. Register A1h
7 6 5 4 3 2 1 0
JESD_SH_STATE_PREV
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-360. Register A1 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SH_STATE
_PREV
R 0h
JESDB: Previous K28.5 SEARCH_PATTERN_STATE value
JESDC: Previous SYNC_HEADER
SEARCH_PATTERN_STATE value
bits(1:0) = SRX1/SRX5
bits(3:2) = SRX2/SRX6
bits(5:4) = SRX3/SRX7
bits(7:6) = SRX4/SRX8
For stable link, the bits for each lane enabled should read as
"01"
Note: Refer to the TI application note for details on error
interpretation.