IO Wrap Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.16.464 Register 87Dh (offset = 87Dh) [reset = 2h]
Figure 2-2727. Register 87Dh
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_RXD_DSA_
GAIN_0
OVR_INTPI_R
XD_DSA_GAIN
_0
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2743. Register 87D Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
RXD_DSA_GAIN_
0
R/W 1h
control to select whether the input function
intpi_rxd_dsa_gain_0 needs to be overriden ot not. 1 indicates
override.
0-0
OVR_INTPI_RXD_
DSA_GAIN_0
R/W 0h override value for ovr_sel_intpi_rxd_dsa_gain_0 is made high
2.16.465 Register 880h (offset = 880h) [reset = 0h]
Figure 2-2728. Register 880h
7 6 5 4 3 2 1 0
SEL_INTPI_RXD_DSA_GAIN_1 POL_INTPI_RX
D_DSA_GAIN_
1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2744. Register 880 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_RXD_
DSA_GAIN_1
R/W 0h
select control for intpi_rxd_dsa_gain_1. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_RXD_
DSA_GAIN_1
R/W 0h
polarity control for intpi_rxd_dsa_gain_1. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.466 Register 881h (offset = 881h) [reset = 2h]
Figure 2-2729. Register 881h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_RXD_DSA_
GAIN_1
OVR_INTPI_R
XD_DSA_GAIN
_1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2745. Register 881 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
RXD_DSA_GAIN_
1
R/W 1h
control to select whether the input function
intpi_rxd_dsa_gain_1 needs to be overriden ot not. 1 indicates
override.
0-0
OVR_INTPI_RXD_
DSA_GAIN_1
R/W 0h override value for ovr_sel_intpi_rxd_dsa_gain_1 is made high
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