ADC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-606. Register 9F Field Descriptions
Bit Field Type Reset Description
7-3 0 R/W 0h Must read or write 0
2-0
LINK1_JESD_TES
T_SEQ_SEL
R/W 0h
JESD test sequence select for STX2/6
Test sequence select:
000=test sequence disabled
001=repeat /D.21.5/ high freq pattern for random jitter (RJ)
010=repeat /K.28.5/ mixed freq pattern for deterministic jitter
(DJ)
011=repeat initial lane alignment (ILA) sequence
100=modified random pattern (modified RPAT / CRPAT)
101=scrambled jitter pattern (JSPAT)
110=repeat /K.28.7/ low freq pattern
111=send short test pattern reg data
2.5.106 Register A0h (offset = A0h) [reset = 0h]
Figure 2-602. Register A0h
7 6 5 4 3 2 1 0
LINK1_INIT_O_MF_COUNTER[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-607. Register A0 Field Descriptions
Bit Field Type Reset Description
7-0
LINK1_INIT_O_MF
_COUNTER[7:0]
R/W 0h
Config for STX2/6
In JESD-B. Register is used as init value of o_mf_counter in
sysref block
In JESD-C,
[4:0] - used to reset blk_ctr
[9:5] - used to reset mblk_ctr
Value has to be multiples of 8. All values cannot be handled
due to assumption of frame_end and multiframe_end in a
specific pattern
2.5.107 Register A1h (offset = A1h) [reset = 0h]
Figure 2-603. Register A1h
7 6 5 4 3 2 1 0
0 0 0 LINK1_INIT_O_MF_COUNTER[12:8]
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-608. Register A1 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
LINK1_INIT_O_MF
_COUNTER[12:8]
R/W 0h
Config for STX2/6
In JESD-B. Register is used as init value of o_mf_counter in
sysref block
In JESD-C,
[4:0] - used to reset blk_ctr
[9:5] - used to reset mblk_ctr
Value has to be multiples of 8. All values cannot be handled
due to assumption of frame_end and multiframe_end in a
specific pattern
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