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JESD_SUBCHIP Register Map
229
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-168. Register CF Field Descriptions
Bit Field Type Reset Description
7-4
MUX_SEL_FOR_T
XB_B1_Q
R/W 3h
Selects the JESD stream that is to be routed to jesd
TXB_B1_Q
0 : sel 2T0_TXA_B0_Q
1 : sel 2T0_TXA_B1_Q
2 : sel 2T0_TXB_B0_Q
3 : sel 2T0_TXB_B1_Q
4 : sel 2T0_TXC_B0_Q
5 : sel 2T0_TXC_B1_Q
6 : sel 2T0_TXD_B0_Q
7 : sel 2T0_TXD_B1_Q
8 : sel 2T1_TXA_B0_Q
9 : sel 2T1_TXA_B1_Q
10 : sel 2T1_TXB_B0_Q
11 : sel 2T1_TXB_B1_Q
12 : sel 2T1_TXC_B0_Q
13 : sel 2T1_TXC_B1_Q
14 : sel 2T1_TXD_B0_Q
15 : sel 2T1_TXD_B1_Q
Refer to the configuration guide for mode details.
3-0
MUX_SEL_FOR_T
XB_B1_I
R/W 3h
Selects the JESD stream that is to be routed to jesd
TXB_B1_I
0 : sel 2T0_TXA_B0_I
1 : sel 2T0_TXA_B1_I
2 : sel 2T0_TXB_B0_I
3 : sel 2T0_TXB_B1_I
4 : sel 2T0_TXC_B0_I
5 : sel 2T0_TXC_B1_I
6 : sel 2T0_TXD_B0_I
7 : sel 2T0_TXD_B1_I
8 : sel 2T1_TXA_B0_I
9 : sel 2T1_TXA_B1_I
10 : sel 2T1_TXB_B0_I
11 : sel 2T1_TXB_B1_I
12 : sel 2T1_TXC_B0_I
13 : sel 2T1_TXC_B1_I
14 : sel 2T1_TXD_B0_I
15 : sel 2T1_TXD_B1_I
Refer to the configuration guide for mode details.
2.3.125 Register D0h (offset = D0h) [reset = 44h]
Figure 2-166. Register D0h
7 6 5 4 3 2 1 0
MUX_SEL_FOR_TXC_B0_Q MUX_SEL_FOR_TXC_B0_I
R/W-4h R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset