Texas Instruments AFE79 Series - 2.3.33 Register 47 h (offset = 47 h) [reset = 50 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-76. Register 46 Field Descriptions (continued)
Bit Field Type Reset Description
5-4
MUX_SEL_FBAB_I
1_FOR_2R1F_CD
R/W 3h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbab_2
0 : fbcd_i_s0
1 : fbcd_i_s1
2 : fbab_i_s0
3 : fbab_i_s1
Using LATTE to configure this register is recommended.
3-2
MUX_SEL_FBAB_
Q0_FOR_2R1F_C
D
R/W 2h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbab_1
0 : fbcd_q_s0
1 : fbcd_q_s1
2 : fbab_q_s0
3 : fbab_q_s1
Using LATTE to configure this register is recommended.
1-0
MUX_SEL_FBAB_I
0_FOR_2R1F_CD
R/W 2h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbab_0
0 : fbcd_i_s0
1 : fbcd_i_s1
2 : fbab_i_s0
3 : fbab_i_s1
Using LATTE to configure this register is recommended.
2.3.33 Register 47h (offset = 47h) [reset = 50h]
Figure 2-74. Register 47h
7 6 5 4 3 2 1 0
MUX_SEL_FBCD_Q1_FOR_2R1
F_CD
MUX_SEL_FBCD_I1_FOR_2R1
F_CD
MUX_SEL_FBCD_Q0_FOR_2R1
F_CD
MUX_SEL_FBCD_I0_FOR_2R1
F_CD
R/W-1h R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-77. Register 47 Field Descriptions
Bit Field Type Reset Description
7-6
MUX_SEL_FBCD_
Q1_FOR_2R1F_C
D
R/W 1h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbcd_3
0 : fbcd_q_s0
1 : fbcd_q_s1
2 : fbab_q_s0
3 : fbab_q_s1
Using LATTE to configure this register is recommended.
5-4
MUX_SEL_FBCD_I
1_FOR_2R1F_CD
R/W 1h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbcd_2
0 : fbcd_i_s0
1 : fbcd_i_s1
2 : fbab_i_s0
3 : fbab_i_s1
Using LATTE to configure this register is recommended.