Texas Instruments AFE79 Series User Manual

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-657. Register E1 Field Descriptions (continued)
Bit Field Type Reset Description
1-0
RXA_SD_CLK_DIV
_M
R/W 2h
If input is 2 samples per clk:
SD by 2 -> M=1, N=1
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=2
if input is 1 sample per clk:
SD by 2 -> M=1, N=2
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=4
2.5.157 Register E2h (offset = E2h) [reset = 6h]
Figure 2-653. Register E2h
7 6 5 4 3 2 1 0
0 0 0 0 RXB_SD_CLK_DIV_N_M1 RXB_SD_CLK_DIV_M
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-658. Register E2 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-2
RXB_SD_CLK_DIV
_N_M1
R/W 1h
If input is 2 samples per clk:
SD by 2 -> M=1, N=1
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=2
if input is 1 sample per clk:
SD by 2 -> M=1, N=2
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=4
1-0
RXB_SD_CLK_DIV
_M
R/W 2h
If input is 2 samples per clk:
SD by 2 -> M=1, N=1
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=2
if input is 1 sample per clk:
SD by 2 -> M=1, N=2
SD by 3 -> M=1, N=3
SD by 4 -> M=1, N=4
2.5.158 Register E3h (offset = E3h) [reset = 6h]
Figure 2-654. Register E3h
7 6 5 4 3 2 1 0
0 0 0 0 FBAB_SD_CLK_DIV_N_M1 FBAB_SD_CLK_DIV_M
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English