Texas Instruments AFE79 Series - 2.13.7 Register 49 h (offset = 49 h) [reset = 4 h]; 2.13.8 Register 4 Ah (offset = 4 Ah) [reset = 1 h]; 2.13.9 Register 4 Eh (offset = 4 Eh) [reset = 6 h]; 2.13.10 Register 60 h (offset = 60 h) [reset = 44 h]

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Serial Interface Register Maps
2.13.7 Register 49h (offset = 49h) [reset = 4h]
Figure 2-1419. Register 49h
7 6 5 4 3 2 1 0
RX_DDC_FIFO_CONFIG1
R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1432. Register 49 Field Descriptions
Bit Field Type Reset Description
4-0
RX_DDC_FIFO_C
ONFIG1
R/W 4h
RX DDC FIFO Configuration1. Value dependent on
decimation factor. Optimal value automatically determined if
System Configuration Macros are used.
2.13.8 Register 4Ah (offset = 4Ah) [reset = 1h]
Figure 2-1420. Register 4Ah
7 6 5 4 3 2 1 0
RX_DDC_FIFO_CONFIG2
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1433. Register 4A Field Descriptions
Bit Field Type Reset Description
2-0
RX_DDC_FIFO_C
ONFIG2
R/W 1h
RX DDC FIFO Configuration2. Value dependent on
decimation factor. Optimal value automatically determined if
System Configuration Macros are used.
2.13.9 Register 4Eh (offset = 4Eh) [reset = 6h]
Figure 2-1421. Register 4Eh
7 6 5 4 3 2 1 0
RX_DDC_MISC_DLY_CONFIG
R/W-6h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1434. Register 4E Field Descriptions
Bit Field Type Reset Description
2-0
RX_DDC_MISC_D
LY_CONFIG
R/W 6h
Latency-matching delay controls in different RX DDC sections.
Optimal value automatically determined if System
Configuration Macros are used.
2.13.10 Register 60h (offset = 60h) [reset = 44h]
Figure 2-1422. Register 60h
7 6 5 4 3 2 1 0
RX_DDC_ASYNC_FIFO_CONFIG0
R/W-44h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset