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871
SBAU337–May 2020
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Serial Interface Register Maps
2.14.38 Register 105h (offset = 105h) [reset = 0h]
Figure 2-1921. Register 105h
7 6 5 4 3 2 1 0
FB_DDC_NCO1_FMULT[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1935. Register 105 Field Descriptions
Bit Field Type Reset Description
7-0
FB_DDC_NCO1_F
MULT[15:8]
R/W 0h
Frequency shift corresponding to the fcw of nco1, expressed
in kHz, modulo Fadc/16. Value programmed here should
correspond to the nco0 fcw, and should be a value between [0
and Fadc/16].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
2.14.39 Register 106h (offset = 106h) [reset = 0h]
Figure 2-1922. Register 106h
7 6 5 4 3 2 1 0
FB_DDC_NCO1_FMULT[21:16]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1936. Register 106 Field Descriptions
Bit Field Type Reset Description
5-0
FB_DDC_NCO1_F
MULT[21:16]
R/W 0h
Frequency shift corresponding to the fcw of nco1, expressed
in kHz, modulo Fadc/16. Value programmed here should
correspond to the nco0 fcw, and should be a value between [0
and Fadc/16].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
2.14.40 Register 108h (offset = 108h) [reset = 0h]
Figure 2-1923. Register 108h
7 6 5 4 3 2 1 0
FB_DDC_NCO2_FMULT[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1937. Register 108 Field Descriptions
Bit Field Type Reset Description
7-0
FB_DDC_NCO2_F
MULT[7:0]
R/W 0h
Frequency shift corresponding to the fcw of nco2, expressed
in kHz, modulo Fadc/16. Value programmed here should
correspond to the nco0 fcw, and should be a value between [0
and Fadc/16].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
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