Texas Instruments AFE79 Series - 2.3.161 Register 182 h (offset = 182 h) [reset = 0 h]; 2.3.162 Register 183 h (offset = 183 h) [reset = 0 h]; 2.3.163 Register 188 h (offset = 188 h) [reset = 0 h]; 2.3.164 Register 189 h (offset = 189 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.3.161 Register 182h (offset = 182h) [reset = 0h]
Figure 2-202. Register 182h
7 6 5 4 3 2 1 0
DAC_SYNC_N_TO_PIN
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-205. Register 182 Field Descriptions
Bit Field Type Reset Description
3-0
DAC_SYNC_N_TO
_PIN
R 0h Spi monitor of dac_sync_n output ports
2.3.162 Register 183h (offset = 183h) [reset = 0h]
Figure 2-203. Register 183h
7 6 5 4 3 2 1 0
DAC_SYNC_N_PRE_MUX
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-206. Register 183 Field Descriptions
Bit Field Type Reset Description
7-0
DAC_SYNC_N_PR
E_MUX
R 0h Spi monitor of dac_sync_n pins from lanes before sync_n mux
2.3.163 Register 188h (offset = 188h) [reset = 0h]
Figure 2-204. Register 188h
7 6 5 4 3 2 1 0
DBG_RX_READ_OUT_REG1[7:0]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-207. Register 188 Field Descriptions
Bit Field Type Reset Description
7-0
DBG_RX_READ_O
UT_REG1[7:0]
R 0h
Data from first 4R mux output i.e.
mux_sel_rxa_b1_i_for_2r1f_ab, is sent to this status register,
to check for data toggling.
dbg_rx_read_out_reg1 and dbg_rx_read_out_reg2 has two
consecutive samples
2.3.164 Register 189h (offset = 189h) [reset = 0h]
Figure 2-205. Register 189h
7 6 5 4 3 2 1 0
DBG_RX_READ_OUT_REG1[15:8]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset