Macro Operand Registers
Macro Memory
Macro Status Register
Macro Result Registers
2 x 32b
18 x 32b
20 x 32b
1k x 32b
Macro Opcode Register
Opcode
Results
Status
Operand
1 x 8b
Large Data
67
SBAU337–May 2020
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Copyright © 2020, Texas Instruments Incorporated
Macro
Chapter 1
SBAU337–May 2020
Macro
1.1 Design Details
AFE79xx provides a set of Macro Interfaces for control and configuration of the chip. Macro commands
abstract out the internal device configuration sequence to a simple set of configurations and thus simplify
the host interaction. Macro commands are triggered via regular register writes to AFE79xx through SPI.
The AFE79xx is always a slave on the SPI and the Host is the master on the SPI. This document
describes the Macro Interface protocol and lists the commands along with their functionality.
1.1.1 Macro Interface Protocol
The Macro execution has two phases – Macro command initiation and Macro command response. The
Macro command is initiated by the Host by writing to a fixed set of registers using the Serial Peripheral
Interface (SPI) and the Macro command response is given by AFE79xx through interrupts and status
registers.
See Section 2.8 section for Register Address mapping.
Figure 1-1. AFE79xx Macro Interface
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