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RX Top Register Map
841
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-1864. Register 5E7 Field Descriptions
Bit Field Type Reset Description
5-0
RX_AGC_MIN_DV
GA_ATTN_USED
R 0h
Min dvga attn seen by stat module. This is in 0.5 dB
resolution.
2.13.440 Register 5E8h (offset = 5E8h) [reset = 0h]
Figure 2-1852. Register 5E8h
7 6 5 4 3 2 1 0
RX_AGC_BAN
D1_CURR_EX
T_LNA_BYPAS
S
RX_AGC_BAN
D0_CURR_EX
T_LNA_BYPAS
S
RX_AGC_CURR_DVGA_ATTN
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1865. Register 5E8 Field Descriptions
Bit Field Type Reset Description
7-7
RX_AGC_BAND1_
CURR_EXT_LNA_
BYPASS
R 0h
Current external LNA control for Band1
0 : Ext LNA is Enabled
1 : Ext LNA is Bypassed
6-6
RX_AGC_BAND0_
CURR_EXT_LNA_
BYPASS
R 0h
Current external LNA control for Band0
0 : Ext LNA is Enabled
1 : Ext LNA is Bypassed
5-0
RX_AGC_CURR_
DVGA_ATTN
R 0h
Current value of External DVGA attn. This is in 0.5 dB
resolution.
2.13.441 Register 5E9h (offset = 5E9h) [reset = 0h]
Figure 2-1853. Register 5E9h
7 6 5 4 3 2 1 0
RX_AGC_CURR_ATTN
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1866. Register 5E9 Field Descriptions
Bit Field Type Reset Description
5-0
RX_AGC_CURR_A
TTN
R 0h DSA attn read out. This is in 0.5 dB resolution.
2.13.442 Register 5EAh (offset = 5EAh) [reset = 0h]
Figure 2-1854. Register 5EAh
7 6 5 4 3 2 1 0
reserved RX_AGC_ATT
N_CHANGED
RX_AGC_BAN
D1_LNA_BYPA
SS_CHANGED
RX_AGC_BAN
D0_LNA_BYPA
SS_CHANGED
R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset