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IO Wrap Register Map
1177
SBAU337–May 2020
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Serial Interface Register Maps
2.16.538 Register A11h (offset = A11h) [reset = 2h]
Figure 2-2801. Register A11h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TX_GAIN_S
W_1
OVR_INTPI_TX
_GAIN_SW_1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2817. Register A11 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TX_GAIN_SW_1
R/W 1h
control to select whether the input function intpi_tx_gain_sw_1
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TX_G
AIN_SW_1
R/W 0h override value for ovr_sel_intpi_tx_gain_sw_1 is made high
2.16.539 Register A14h (offset = A14h) [reset = 0h]
Figure 2-2802. Register A14h
7 6 5 4 3 2 1 0
SEL_INTPI_TX_GAIN_SW_2 POL_INTPI_TX
_GAIN_SW_2
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2818. Register A14 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_TX_G
AIN_SW_2
R/W 0h
select control for intpi_tx_gain_sw_2. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_TX_G
AIN_SW_2
R/W 0h
polarity control for intpi_tx_gain_sw_2. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.540 Register A15h (offset = A15h) [reset = 2h]
Figure 2-2803. Register A15h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TX_GAIN_S
W_2
OVR_INTPI_TX
_GAIN_SW_2
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2819. Register A15 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TX_GAIN_SW_2
R/W 1h
control to select whether the input function intpi_tx_gain_sw_2
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TX_G
AIN_SW_2
R/W 0h override value for ovr_sel_intpi_tx_gain_sw_2 is made high
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