Texas Instruments AFE79 Series - 2.4.17 Register 30 h (offset = 30 h) [reset = 1 h]; 2.4.18 Register 31 h (offset = 31 h) [reset = 0 h]; 2.4.19 Register 32 h (offset = 32 h) [reset = 1 h]; 2.4.20 Register 33 h (offset = 33 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.4.17 Register 30h (offset = 30h) [reset = 1h]
Figure 2-246. Register 30h
7 6 5 4 3 2 1 0
DUC_CLK_TX1_DIV_M
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-250. Register 30 Field Descriptions
Bit Field Type Reset Description
4-0
DUC_CLK_TX1_DI
V_M
R/W 1h
For lanes[0:1]/[4:5], M-value in Divide ratio of M/N for
generating the DUC_WR_CLK for DAC_JESD from
ROOT_CLK.
2.4.18 Register 31h (offset = 31h) [reset = 0h]
Figure 2-247. Register 31h
7 6 5 4 3 2 1 0
DUC_CLK_TX1_DIV_N_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-251. Register 31 Field Descriptions
Bit Field Type Reset Description
4-0
DUC_CLK_TX1_DI
V_N_M1
R/W 0h
For lanes[0:1]/[4:5], N_M1 value in Divide ratio of M/N for
generating the DUC_WR_CLK for DAC_JESD from
ROOT_CLK.
2.4.19 Register 32h (offset = 32h) [reset = 1h]
Figure 2-248. Register 32h
7 6 5 4 3 2 1 0
DUC_CLK_TX2_DIV_M
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-252. Register 32 Field Descriptions
Bit Field Type Reset Description
4-0
DUC_CLK_TX2_DI
V_M
R/W 1h
For lanes[2:3]/[6:7], M-value in Divide ratio of M/N for
generating the DUC_WR_CLK for DAC_JESD from
ROOT_CLK.
2.4.20 Register 33h (offset = 33h) [reset = 0h]
Figure 2-249. Register 33h
7 6 5 4 3 2 1 0
DUC_CLK_TX2_DIV_N_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset