Texas Instruments AFE79 Series - 2.14.142 Register 4 B2 h (offset = 4 B2 h) [reset = 40 h]; 2.14.143 Register 4 B3 h (offset = 4 B3 h) [reset = 10 h]; 2.14.144 Register 4 B4 h (offset = 4 B4 h) [reset = 2 h]

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Serial Interface Register Maps
2.14.142 Register 4B2h (offset = 4B2h) [reset = 40h]
Figure 2-2025. Register 4B2h
7 6 5 4 3 2 1 0
FB_AGC_PIN_4_SELECT_BITS[7:0]
R/W-40h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2039. Register 4B2 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_PIN_4_S
ELECT_BITS[7:0]
R/W 40h
Each bit corresponds to one particular detector which should
be used for peak detector 4
Bit 14 --> Dig OVR Bit 13 -> Reserved Bit 12 --> Reserved Bit
11 --> LNARF det Bit 10 --> Reserved Bit 9 --> Reserved Bit 8
--> reserved Bit 7 --> Dig bigstep attack Bit 6 --> Dig small
step attack Bit 5 --> Bigstep decay Bit 4 --> Small step decay
Bit 3 --> Dig pwr attack Bit 2 --> Dig pwr decay Bit 1 -->
Absolute reliability Bit 0 --> Relative reliability
2.14.143 Register 4B3h (offset = 4B3h) [reset = 10h]
Figure 2-2026. Register 4B3h
7 6 5 4 3 2 1 0
FB_AGC_PIN_4_SELECT_BITS[15:8]
R/W-10h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2040. Register 4B3 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_PIN_4_S
ELECT_BITS[15:8]
R/W 10h
Each bit corresponds to one particular detector which should
be used for peak detector 4
Bit 14 --> Dig OVR Bit 13 -> Reserved Bit 12 --> Reserved Bit
11 --> LNARF det Bit 10 --> Reserved Bit 9 --> Reserved Bit 8
--> reserved Bit 7 --> Dig bigstep attack Bit 6 --> Dig small
step attack Bit 5 --> Bigstep decay Bit 4 --> Small step decay
Bit 3 --> Dig pwr attack Bit 2 --> Dig pwr decay Bit 1 -->
Absolute reliability Bit 0 --> Relative reliability
2.14.144 Register 4B4h (offset = 4B4h) [reset = 2h]
Figure 2-2027. Register 4B4h
7 6 5 4 3 2 1 0
FB_AGC_GAIN_CHG_PULSE_EXPN_COUNT[7:0]
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2041. Register 4B4 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_GAIN_C
HG_PULSE_EXPN
_COUNT[7:0]
R/W 2h
Number of clock cycles (in terms of Fs/8) by which a high(one)
should be extended before being sent on the pins for gain
change indication pin.