Texas Instruments AFE79 Series - 2.13.25 Register 100 h (offset = 100 h) [reset = 0 h]; 2.13.26 Register 101 h (offset = 101 h) [reset = 0 h]; 2.13.27 Register 102 h (offset = 102 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-1449. Register E3 Field Descriptions
Bit Field Type Reset Description
7-0
RX_DDC_BAND0_
NCO1_PHASE_OF
FSET[15:8]
R/W 0h Offset phase for nco1 of band0
2.13.25 Register 100h (offset = 100h) [reset = 0h]
Figure 2-1437. Register 100h
7 6 5 4 3 2 1 0
RX_DDC_BAND0_NCO0_FMULT[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1450. Register 100 Field Descriptions
Bit Field Type Reset Description
7-0
RX_DDC_BAND0_
NCO0_FMULT[7:0]
R/W 0h
Frequency shift corresponding to the fcw of nco0 of band0,
expressed in kHz, less the closest multiple of Fadc/16. Value
programmed here should correspond to the nco0 fcw of
band0, and should be a value between [-Fadc/32 and
+Fadc/32].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
2.13.26 Register 101h (offset = 101h) [reset = 0h]
Figure 2-1438. Register 101h
7 6 5 4 3 2 1 0
RX_DDC_BAND0_NCO0_FMULT[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1451. Register 101 Field Descriptions
Bit Field Type Reset Description
7-0
RX_DDC_BAND0_
NCO0_FMULT[15:
8]
R/W 0h
Frequency shift corresponding to the fcw of nco0 of band0,
expressed in kHz, less the closest multiple of Fadc/16. Value
programmed here should correspond to the nco0 fcw of
band0, and should be a value between [-Fadc/32 and
+Fadc/32].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
2.13.27 Register 102h (offset = 102h) [reset = 0h]
Figure 2-1439. Register 102h
7 6 5 4 3 2 1 0
RX_DDC_BAND0_NCO0_FMULT[21:16]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset