DAC JESD Register Map
www.ti.com
278
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.37 Register 44h (offset = 44h) [reset = 0h]
Figure 2-266. Register 44h
7 6 5 4 3 2 1 0
LINK0_DID
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-270. Register 44 Field Descriptions
Bit Field Type Reset Description
7-0 LINK0_DID R/W 0h Lane configuration
2.4.38 Register 45h (offset = 45h) [reset = 0h]
Figure 2-267. Register 45h
7 6 5 4 3 2 1 0
LINK0_BID LINK0_ADJCNT
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-271. Register 45 Field Descriptions
Bit Field Type Reset Description
7-4 LINK0_BID R/W 0h Lane configuration
3-0 LINK0_ADJCNT R/W 0h Lane configuration
2.4.39 Register 46h (offset = 46h) [reset = 0h]
Figure 2-268. Register 46h
7 6 5 4 3 2 1 0
LINK0_ADJDIR LINK0_PHADJ
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-272. Register 46 Field Descriptions
Bit Field Type Reset Description
6-6 LINK0_ADJDIR R/W 0h Lane configuration
5-5 LINK0_PHADJ R/W 0h Lane configuration
2.4.40 Register 47h (offset = 47h) [reset = 1h]
Figure 2-269. Register 47h
7 6 5 4 3 2 1 0
LINK0_SCR LINK0_ILA_L_M1
R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset