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Texas Instruments AFE79 Series - 2.3.149 Register 16 Ah (offset = 16 Ah) [reset = 0 h]; 2.3.150 Register 16 Ch (offset = 16 Ch) [reset = 0 h]; 2.3.151 Register 16 Dh (offset = 16 Dh) [reset = 0 h]

Texas Instruments AFE79 Series
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JESD_SUBCHIP Register Map
www.ti.com
242
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.3.149 Register 16Ah (offset = 16Ah) [reset = 0h]
Figure 2-190. Register 16Ah
7 6 5 4 3 2 1 0
DBG_FBCD_ASYNC_FIFO_ALARM_MASK DBG_FBAB_ASYNC_FIFO_ALARM_MASK
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-193. Register 16A Field Descriptions
Bit Field Type Reset Description
7-4
DBG_FBCD_ASYN
C_FIFO_ALARM_
MASK
R/W 0h
mask for FBCD to JESD Async-FIFO debug alarm. Only bit0
is valid.
3-0
DBG_FBAB_ASYN
C_FIFO_ALARM_
MASK
R/W 0h
mask for FBAB to JESD Async-FIFO debug alarm. Only bit0 is
valid.
2.3.150 Register 16Ch (offset = 16Ch) [reset = 0h]
Figure 2-191. Register 16Ch
7 6 5 4 3 2 1 0
DBG_RXB_ASYNC_FIFO_ALARM DBG_RXA_ASYNC_FIFO_ALARM
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-194. Register 16C Field Descriptions
Bit Field Type Reset Description
7-4
DBG_RXB_ASYNC
_FIFO_ALARM
R 0h
overflow/underflow flag for RX-B to JESD Async fifo. Only bit0
is valid.
3-0
DBG_RXA_ASYNC
_FIFO_ALARM
R 0h
overflow/underflow flag for RX-A to JESD Async fifo. Only bit0
is valid.
2.3.151 Register 16Dh (offset = 16Dh) [reset = 0h]
Figure 2-192. Register 16Dh
7 6 5 4 3 2 1 0
DBG_RXD_ASYNC_FIFO_ALARM DBG_RXC_ASYNC_FIFO_ALARM
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-195. Register 16D Field Descriptions
Bit Field Type Reset Description
7-4
DBG_RXD_ASYN
C_FIFO_ALARM
R 0h
overflow/underflow flag for RX-D to JESD Async fifo. Only bit0
is valid.
3-0
DBG_RXC_ASYN
C_FIFO_ALARM
R 0h
overflow/underflow flag for RX-C to JESD Async fifo. Only bit0
is valid.

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