DSA Page 0 Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-1107. Register 7C Field Descriptions
Bit Field Type Reset Description
5-0
SPI_AGC_DSA_FB
_1
R/W 0h
dsa value when fbmuxsel indicates txb is fedback to this
channel.
2.9.7 Register 80h (offset = 80h) [reset = 0h]
Figure 2-1099. Register 80h
7 6 5 4 3 2 1 0
SPI_AGC_DSA_FB_2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1108. Register 80 Field Descriptions
Bit Field Type Reset Description
5-0
SPI_AGC_DSA_FB
_2
R/W 0h
dsa value when fbmuxsel indicates txc is fedback to this
channel.
2.9.8 Register 84h (offset = 84h) [reset = 0h]
Figure 2-1100. Register 84h
7 6 5 4 3 2 1 0
SPI_AGC_DSA_FB_3
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1109. Register 84 Field Descriptions
Bit Field Type Reset Description
5-0
SPI_AGC_DSA_FB
_3
R/W 0h
dsa value when fbmuxsel indicates txd is fedback to this
channel.
2.9.9 Register C8h (offset = C8h) [reset = 0h]
Figure 2-1101. Register C8h
7 6 5 4 3 2 1 0
TXA_DSA_FINE TXA_DSA_INDEX
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1110. Register C8 Field Descriptions
Bit Field Type Reset Description
7-6 TXA_DSA_FINE R/W 0h
Two bit fine gain ctrl. When fc_mode_txa is '1' this directly
becomes the fc code.
5-0 TXA_DSA_INDEX R/W 0h
Write to this register automatically trigger change pulse to
applied. SO the register is always placed at 'd200. There is a
mask which can gate this behavior. Mask exists for all the gain
registers, which can be used to get the desired behavior The
mask registers are in spiA page.
By deault all masks are disabled.
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