DAC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.4.189 Register F5h (offset = F5h) [reset = 0h]
Figure 2-418. Register F5h
7 6 5 4 3 2 1 0
JESD_SYSREF_DIV2_TX2_FLAG JESD_CLK_DIV2_TX2_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-422. Register F5 Field Descriptions
Bit Field Type Reset Description
7-4
JESD_SYSREF_DI
V2_TX2_FLAG
R 0h jesd_rx_div2_sysref monitor flag
3-0
JESD_CLK_DIV2_
TX2_FLAG
R 0h jesd_rx_div2_clk monitor flag
2.4.190 Register F6h (offset = F6h) [reset = 0h]
Figure 2-419. Register F6h
7 6 5 4 3 2 1 0
DUC_SYSREF_TX2_FLAG DUC_CLK_TX2_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-423. Register F6 Field Descriptions
Bit Field Type Reset Description
7-4
DUC_SYSREF_TX
2_FLAG
R 0h duc_wr_sysref monitor flag
3-0
DUC_CLK_TX2_FL
AG
R 0h duc_wr_clk monitor flag
2.4.191 Register F8h (offset = F8h) [reset = 0h]
Figure 2-420. Register F8h
7 6 5 4 3 2 1 0
ALARMS_MASK[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-424. Register F8 Field Descriptions
Bit Field Type Reset Description
7-0
ALARMS_MASK[7:
0]
R/W 0h
Masks 'alarms' register to the alarm pin; will not affect alarm
read from SPI
[3:0] = TIED to 0
[4] = JESD shorttest alarm
[5] = TIED to 0
[6] = serdesab_pll_loss_of_lock
[7] = serdescd_pll_loss_of_lock
Note: Refer to the TI application note for details on error
interpretation.