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ADC JESD Register Map
423
SBAU337–May 2020
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Serial Interface Register Maps
2.5.108 Register A2h (offset = A2h) [reset = 0h]
Figure 2-604. Register A2h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 LINK1_ERR_C
NT_CLR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-609. Register A2 Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
LINK1_ERR_CNT_
CLR
R/W 0h
Config for STX2/6
Clears the JESD sync_n error counter
2.5.109 Register A4h (offset = A4h) [reset = 0h]
Figure 2-605. Register A4h
7 6 5 4 3 2 1 0
LINK2_DID
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-610. Register A4 Field Descriptions
Bit Field Type Reset Description
7-0 LINK2_DID R/W 0h JESD link config for STX 3,4/7,8
2.5.110 Register A5h (offset = A5h) [reset = 0h]
Figure 2-606. Register A5h
7 6 5 4 3 2 1 0
LINK2_ADJCNT LINK2_BID
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-611. Register A5 Field Descriptions
Bit Field Type Reset Description
7-4 LINK2_ADJCNT R/W 0h JESD link config for STX 3,4/7,8
3-0 LINK2_BID R/W 0h JESD link config for STX 3,4/7,8
2.5.111 Register A6h (offset = A6h) [reset = 0h]
Figure 2-607. Register A6h
7 6 5 4 3 2 1 0
0 LINK2_ADJDIR LINK2_PHADJ 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset