ADC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.5.129 Register BAh (offset = BAh) [reset = 0h]
Figure 2-625. Register BAh
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 LINK2_ERR_C
NT_CLR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-630. Register BA Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
LINK2_ERR_CNT_
CLR
R/W 0h
Config for STX 3,4/7,8
Clears the JESD sync_n error counter
2.5.130 Register BCh (offset = BCh) [reset = 0h]
Figure 2-626. Register BCh
7 6 5 4 3 2 1 0
0 0 0 LID0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-631. Register BC Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0 LID0 R/W 0h JESD link config for STX1/5
2.5.131 Register BDh (offset = BDh) [reset = 1h]
Figure 2-627. Register BDh
7 6 5 4 3 2 1 0
0 0 0 LID1
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-632. Register BD Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0 LID1 R/W 1h
JESD link config for STX2/6
min : 1
2.5.132 Register BEh (offset = BEh) [reset = 2h]
Figure 2-628. Register BEh
7 6 5 4 3 2 1 0
0 0 0 LID2
R/W-0h R/W-0h R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset