Texas Instruments AFE79 Series - 2.5.91 Register 8 Fh (offset = 8 Fh) [reset = 1 h]; 2.5.92 Register 90 h (offset = 90 h) [reset = 1 h]; 2.5.93 Register 91 h (offset = 91 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.91 Register 8Fh (offset = 8Fh) [reset = 1h]
Figure 2-587. Register 8Fh
7 6 5 4 3 2 1 0
LINK1_SCR 0 0 LINK1_ILA_L_M1
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-592. Register 8F Field Descriptions
Bit Field Type Reset Description
7-7 LINK1_SCR R/W 0h
JESD link config for STX2/6
For JESD-B/C
When 1, scrambler (present between transport layer and link
layer) is enabled
1+x^14+x^15
0 : scrambler disabled
1 : scrambler enabled
6-5 0 R/W 0h Must read or write 0
4-0 LINK1_ILA_L_M1 R/W 1h
JESD link config for STX2/6
Used only when link1_jesd_ila_config_override is 1.
Else L derived from LMFS is used.
2.5.92 Register 90h (offset = 90h) [reset = 1h]
Figure 2-588. Register 90h
7 6 5 4 3 2 1 0
LINK1_ILA_F_M1
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-593. Register 90 Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_ILA_F_M1 R/W 1h
JESD link config for STX2/6
Used only when link1_jesd_ila_config_override is 1.
Else F derived from LMFS is used.
2.5.93 Register 91h (offset = 91h) [reset = 0h]
Figure 2-589. Register 91h
7 6 5 4 3 2 1 0
LINK1_ILA_K_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-594. Register 91 Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_ILA_K_M1 R/W 0h
JESD link config for STX2/6
Used only when link1_jesd_ila_config_override is 1.
Else K derived from link1_k_m1 reg