Texas Instruments AFE79 Series - 2.4.21 Register 34 h (offset = 34 h) [reset = 1 h]; 2.4.22 Register 35 h (offset = 35 h) [reset = 0 h]; 2.4.23 Register 36 h (offset = 36 h) [reset = 1 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-253. Register 33 Field Descriptions
Bit Field Type Reset Description
4-0
DUC_CLK_TX2_DI
V_N_M1
R/W 0h
For lanes[2:3]/[6:7], N_M1 value in Divide ratio of M/N for
generating the DUC_WR_CLK for DAC_JESD from
ROOT_CLK.
2.4.21 Register 34h (offset = 34h) [reset = 1h]
Figure 2-250. Register 34h
7 6 5 4 3 2 1 0
JESD_CLK_TX1_DIV_M
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-254. Register 34 Field Descriptions
Bit Field Type Reset Description
4-0
JESD_CLK_TX1_D
IV_M
R/W 1h
For lanes[0:1]/[4:5], M-value in Divide ratio of M/N for
generating the JESD_RX_CLK for DAC_JESD from
ROOT_CLK.
2.4.22 Register 35h (offset = 35h) [reset = 0h]
Figure 2-251. Register 35h
7 6 5 4 3 2 1 0
JESD_CLK_TX1_DIV_N_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-255. Register 35 Field Descriptions
Bit Field Type Reset Description
4-0
JESD_CLK_TX1_D
IV_N_M1
R/W 0h
For lanes[0:1]/[4:5], N_M1 value in Divide ratio of M/N for
generating the JESD_RX_CLK for DAC_JESD from
ROOT_CLK.
2.4.23 Register 36h (offset = 36h) [reset = 1h]
Figure 2-252. Register 36h
7 6 5 4 3 2 1 0
JESD_CLK_TX2_DIV_M
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-256. Register 36 Field Descriptions
Bit Field Type Reset Description
4-0
JESD_CLK_TX2_D
IV_M
R/W 1h
For lanes[2:3]/[6:7], M-value in Divide ratio of M/N for
generating the JESD_RX_CLK for DAC_JESD from
ROOT_CLK.