JESD_SUBCHIP Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.3.59 Register 6Bh (offset = 6Bh) [reset = 76h]
Figure 2-100. Register 6Bh
7 6 5 4 3 2 1 0
RXOCTETPATH7_SEL RXOCTETPATH6_SEL
R/W-7h R/W-6h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-103. Register 6B Field Descriptions
Bit Field Type Reset Description
6-4
RXOCTETPATH7_
SEL
R/W 7h
Selects the input SERDES-Rx lane for data that is normally
supposed to be on SRX8.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2-0
RXOCTETPATH6_
SEL
R/W 6h
Selects the input SERDES-Rx lane for data that is normally
supposed to be on SRX7.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2.3.60 Register 6Ch (offset = 6Ch) [reset = 10h]
Figure 2-101. Register 6Ch
7 6 5 4 3 2 1 0
RXOCTETPATH1_CLK_SEL RXOCTETPATH0_CLK_SEL
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-104. Register 6C Field Descriptions
Bit Field Type Reset Description
6-4
RXOCTETPATH1_
CLK_SEL
R/W 1h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX2.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
RXOCTETPATH0_
CLK_SEL
R/W 0h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX1.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
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