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Texas Instruments AFE79 Series - 2.4.92 Register 7 Bh (offset = 7 Bh) [reset = 0 h]; 2.4.93 Register 7 Ch (offset = 7 Ch) [reset = 3 h]

Texas Instruments AFE79 Series
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DAC JESD Register Map
www.ti.com
296
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.92 Register 7Bh (offset = 7Bh) [reset = 0h]
Figure 2-321. Register 7Bh
7 6 5 4 3 2 1 0
LINK1_ERROR_ENA
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-325. Register 7B Field Descriptions
Bit Field Type Reset Description
7-0
LINK1_ERROR_E
NA
R/W 0h
These bits select the errors generated are counted in the
err_c for the lanes[2:3]/[6:7]. The bits also control what signals
are sent out the pad_syncb pin for error notification.
Each of the bits for the above mentioned lane errors are
mapped to :
bit7 = JESDB: multiframe alignment error
bit6 = JESDB: frame alignment error
bit5 = JESDB: link configuration error
bit4 = JESDB: elastic buffer overflow (bad RBD value)
bit3 = JESDB: elastic buffer match error. The first non-/K/
doesnt match 'match_ctrl' and 'match_data' programmed
values
bit2 = JESDB: code synchronization error
bit1 = JESDB: 8b/10b not-in-table code error
Bit0 = JESDB: 8b/10b disparity error
bit7 = JESDC: EoEMB alignment error
bit6 = JESDC: EoMB alignment error
bit5 = JESDC: cmd-data in crc mode not matching with spi
register bits
bit4 = JESDC: elastic buffer overflow (bad RBD value)
bit3 = JESDC: TIED to 0.
bit2 = JESDC: extended multiblock alignment error
bit1 = JESDC: sync-header invalid error ('11' or '00' received
in expected sync header location)
Bit0 = JESDC: sync-header CRC error
2.4.93 Register 7Ch (offset = 7Ch) [reset = 3h]
Figure 2-322. Register 7Ch
7 6 5 4 3 2 1 0
LINK1_FRAME
_SYNC_ERR_
CNT_CLR
LINK0_FRAME
_SYNC_ERR_
CNT_CLR
LINK1_FRAME
_SYNC_ERR_
ENA
LINK0_FRAME
_SYNC_ERR_
ENA
LINK1_FRAME
_SYNC_ERR_
SYNC_REQUE
ST_ENA
LINK0_FRAME
_SYNC_ERR_
SYNC_REQUE
ST_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-326. Register 7C Field Descriptions
Bit Field Type Reset Description
5-5
LINK1_FRAME_SY
NC_ERR_CNT_CL
R
R/W 0h
For lanes [2:3]/[6:7]
JESDB : To clear error counter caused due to frame sync
error.
JESDC : To clear error counter caused due to fixed-ones
error.
4-4
LINK0_FRAME_SY
NC_ERR_CNT_CL
R
R/W 0h
For lanes [0:1]/[4:5]
JESDB : To clear error counter caused due to frame sync
error.
JESDC : To clear error counter caused due to fixed-ones
error.

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