DAC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-316. Register 72 Field Descriptions
Bit Field Type Reset Description
7-0
LINK1_INIT_O_CO
UNTER
R/W 0h
For Lanes[2:3]/[6:7], on sysref to lmfc, the internal o
counter(JESDB)/mb_counter(JESDC) can be loaded with
init_o_counter value
2.4.84 Register 73h (offset = 73h) [reset = 0h]
Figure 2-313. Register 73h
7 6 5 4 3 2 1 0
LINK1_INIT_F_COUNTER
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-317. Register 73 Field Descriptions
Bit Field Type Reset Description
7-0
LINK1_INIT_F_CO
UNTER
R/W 0h
For Lanes[2:3]/[6:7], on sysref to lmfc, the internal f
counter(JESDB)/emb_counter(JESDC) can be loaded with
init_f_counter value
2.4.85 Register 74h (offset = 74h) [reset = 0h]
Figure 2-314. Register 74h
7 6 5 4 3 2 1 0
LINK1_AUTOL
OAD_JESD_E
RRCNT
LINK0_AUTOL
OAD_JESD_E
RRCNT
LINK1_SYNC_
ERROR_CNT_
CLR
LINK0_SYNC_
ERROR_CNT_
CLR
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-318. Register 74 Field Descriptions
Bit Field Type Reset Description
3-3
LINK1_AUTOLOA
D_JESD_ERRCNT
R/W 0h
For Lanes[2:3]/[6:7], when '1', the error count update is
stopped and captured
2-2
LINK0_AUTOLOA
D_JESD_ERRCNT
R/W 0h
For Lanes[0:1]/[4:5], when '1', the error count update is
stopped and captured
1-1
LINK1_SYNC_ERR
OR_CNT_CLR
R/W 0h
For Lanes[2:3]/[6:7], clears the JESD error count on a rising
edge.
0-0
LINK0_SYNC_ERR
OR_CNT_CLR
R/W 0h
For Lanes[0:1]/[4:5], clears the JESD error count on a rising
edge.
2.4.86 Register 75h (offset = 75h) [reset = C0h]
Figure 2-315. Register 75h
7 6 5 4 3 2 1 0
MATCH_CTRL MATCH_SPECI
FIC
JESD_TEST_SEQ DISABLE_ERR
_REPORT
MP_LINK_ENA NO_LANE_SY
NC
MIN_LATENCY
_ENA
R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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