IO Wrap Register Map
www.ti.com
1184
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.16.559 Register A3Ch (offset = A3Ch) [reset = 0h]
Figure 2-2822. Register A3Ch
7 6 5 4 3 2 1 0
SEL_INTPI_TX_NCOSEL_0 POL_INTPI_TX
_NCOSEL_0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2838. Register A3C Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_TX_N
COSEL_0
R/W 0h
select control for intpi_tx_ncosel_0. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_TX_N
COSEL_0
R/W 0h
polarity control for intpi_tx_ncosel_0. 0 indicates pass through
from GPIO when selected 1 indicates inverted signal
2.16.560 Register A3Dh (offset = A3Dh) [reset = 2h]
Figure 2-2823. Register A3Dh
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TX_NCOSE
L_0
OVR_INTPI_TX
_NCOSEL_0
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2839. Register A3D Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TX_NCOSEL_0
R/W 1h
control to select whether the input function intpi_tx_ncosel_0
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TX_N
COSEL_0
R/W 0h override value for ovr_sel_intpi_tx_ncosel_0 is made high
2.16.561 Register A40h (offset = A40h) [reset = 0h]
Figure 2-2824. Register A40h
7 6 5 4 3 2 1 0
SEL_INTPI_TX_NCOSEL_1 POL_INTPI_TX
_NCOSEL_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2840. Register A40 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_TX_N
COSEL_1
R/W 0h
select control for intpi_tx_ncosel_1. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_TX_N
COSEL_1
R/W 0h
polarity control for intpi_tx_ncosel_1. 0 indicates pass through
from GPIO when selected 1 indicates inverted signal
To Next Page
Loading...
