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Texas Instruments AFE79 Series - 2.4.77 Register 6 Ch (offset = 6 Ch) [reset = 1 Fh]; 2.4.78 Register 6 Dh (offset = 6 Dh) [reset = 1 Fh]; 2.4.79 Register 6 Eh (offset = 6 Eh) [reset = 1 Fh]

Texas Instruments AFE79 Series
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DAC JESD Register Map
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290
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.77 Register 6Ch (offset = 6Ch) [reset = 1Fh]
Figure 2-306. Register 6Ch
7 6 5 4 3 2 1 0
LINK0_K_M1
R/W-1Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-310. Register 6C Field Descriptions
Bit Field Type Reset Description
7-0 LINK0_K_M1 R/W 1Fh
JESDB: The number of frames in a multi-frame for
lanes[0:1]/[4:5]. K should always set to integer multiple of 4.
0<=K-1<32.
JESDC: The number of multiblocks in extended multiblocks for
lanes[0:1]/[4:5]. 0<=K-1<8
2.4.78 Register 6Dh (offset = 6Dh) [reset = 1Fh]
Figure 2-307. Register 6Dh
7 6 5 4 3 2 1 0
LINK1_K_M1
R/W-1Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-311. Register 6D Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_K_M1 R/W 1Fh
JESDB: The number of frames in a multi-frame for
lanes[2:3]/[6:7]. K should always set to integer multiple of 4.
0<=K-1<32.
JESDC: The number of multiblocks in extended multiblocks for
lanes[2:3]/[6:7]. 0<=K-1<8
2.4.79 Register 6Eh (offset = 6Eh) [reset = 1Fh]
Figure 2-308. Register 6Eh
7 6 5 4 3 2 1 0
LINK0_BUFFER_READ_PTR_OFFSET LINK0_BUFFER_DEPTH
R/W-0h R/W-1Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-312. Register 6E Field Descriptions
Bit Field Type Reset Description
7-5
LINK0_BUFFER_R
EAD_PTR_OFFSE
T
R/W 0h UNUSED
4-0
LINK0_BUFFER_D
EPTH
R/W 1Fh elastic buffer depth for lanes[0:1]/[4:5]

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