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SBAU337–May 2020
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Serial Interface Register Maps
2.14.35 Register 101h (offset = 101h) [reset = 0h]
Figure 2-1918. Register 101h
7 6 5 4 3 2 1 0
FB_DDC_NCO0_FMULT[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1932. Register 101 Field Descriptions
Bit Field Type Reset Description
7-0
FB_DDC_NCO0_F
MULT[15:8]
R/W 0h
Frequency shift corresponding to the fcw of nco0, expressed
in kHz, modulo Fadc/16. Value programmed here should
correspond to the nco0 fcw, and should be a value between [0
and Fadc/16].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
2.14.36 Register 102h (offset = 102h) [reset = 0h]
Figure 2-1919. Register 102h
7 6 5 4 3 2 1 0
FB_DDC_NCO0_FMULT[21:16]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1933. Register 102 Field Descriptions
Bit Field Type Reset Description
5-0
FB_DDC_NCO0_F
MULT[21:16]
R/W 0h
Frequency shift corresponding to the fcw of nco0, expressed
in kHz, modulo Fadc/16. Value programmed here should
correspond to the nco0 fcw, and should be a value between [0
and Fadc/16].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
2.14.37 Register 104h (offset = 104h) [reset = 0h]
Figure 2-1920. Register 104h
7 6 5 4 3 2 1 0
FB_DDC_NCO1_FMULT[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1934. Register 104 Field Descriptions
Bit Field Type Reset Description
7-0
FB_DDC_NCO1_F
MULT[7:0]
R/W 0h
Frequency shift corresponding to the fcw of nco1, expressed
in kHz, modulo Fadc/16. Value programmed here should
correspond to the nco0 fcw, and should be a value between [0
and Fadc/16].
The System Configuration Macros automatically compute and
configure this, and are hence strongly recommended.
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